1. Field of the Invention
The present invention relates to so-called QPSK (Quadrature Phase-Shift Keying) and QAM (Quadrature Amplitude Modulation) techniques that allow simultaneous transmission of transmit two binary signals over two carriers of the same frequency but in phase quadrature. The present invention more specifically aims at a rotation correction loop filter in a digital demodulator.
2. Discussion of the Related Art
FIG. 1 shows, in the form of a "constellation", the possible values of two binary signals I and Q to be transmitted. The values of signal I are plotted along a horizontal axis I and the values of signal Q are plotted along a vertical axis Q. In QPSK modulation, each of binary signals I and Q takes a positive value or a negative value of the same amplitude, corresponding to the high and low logic levels. In FIG. 1, points represent the four possible combinations of signals I and Q. These points are normally symmetrical with respect to axes I and Q.
FIG. 2 schematically shows a conventional digital QPSK demodulator. The modulated signal first undergoes a rough analog demodulation. The two components obtained are filtered then provided to analog-to-digital converters 10. Thus, converters 10 respectively provide digital signals I0 and Q0 corresponding to roughly demodulated signals I and Q. As indicated by arrows in FIG. 1, the constellation corresponding to signals I0 and Q0 rotates with respect to the nominal constellation at a speed equal to the frequency error of the rough demodulation.
Thus, to obtain signals I and Q, the constellation has to be rotated in the reverse direction at the same speed. Such is the function of a rotation correction circuit 12 assembled in a phase-locked loop. Rotation correction circuit 12 acts according to a correction signal .PHI. provided by a phase detector 14 which analyzes outputs I and Q of circuit 12. The output of phase detector 14 is first filtered by a digital low-pass filter 16. Phase detector 14 usually provides the difference between signals I and Q, more specifically value Isgn(Q)-Qsgn(I), where sgn(.) is the function "sign of".
Filter 16 generally is a second order filter which includes two amplifiers (multipliers by a constant) 18 and 19 each receiving the output of phase detector 14. An adder 20 receives the output of amplifier 18 and the integral of the output of amplifier 19. The integral is obtained by a digital integrator in the form of a register 22 connected to an adder 24 for accumulating the values provided by amplifier 19.
Signal .PHI. which controls rotation correction circuit 12 is provided by an integrator in the form of a register 26 connected to an adder 28 for accumulating the values provided by adder 20.
Registers 22 and 26 are rated by a clock CK. Clock CK is set to the symbol frequency, that is, to the bit transmission rate of each of signals I and Q.
With this configuration, for each new bit transmitted over signals I and Q, registers 22 and 26 accumulate a new value. In fact, register 22 accumulates frequency values while register 26 accumulates phase values. In steady state, the content of register 22 does not vary, and indicates the frequency error of the rough demodulation, while the content of register 26 continuously varies and represents the phase correction to be brought to the constellation to bring it back to its nominal position (FIG. 1).
To reduce the noise sensitivity of the demodulator, the cut-off frequency of filter 16 is chosen to be particularly small, which reduces the lock-in range and increases the convergence duration of the phase-locked loop. The uncertainty on the carrier frequency of signals I and Q is generally greater than the lock-in range, whereby successive trials must be performed by initializing register 22 to different values to find a lock-in range adapted to the effective carrier frequency.
Since the lock-in range decreases with the symbol frequency, the number of trials to be performed, that is, the number of frequency values to be loaded into register 22, correlatively increases. Further, for each tried frequency, a minimum number of symbols has to be processed before determining whether the loop locks or not, but the symbol rate obviously decreases with the symbol frequency. As a result, the locking time, that is, the time required to find a lock-in range adapted to the carrier frequency, increases in average with the square of the inverse of the symbol frequency.
Taking as an example the reception of satellite transmitted signals, the carrier frequency varies by .+-.5 MHz, the symbol frequency may be set between 1 and 45 Mbits/s, and the lock-in range is on the order of 0.1% of the symbol frequency. Although the carrier frequency has an uncertainty of .+-.5 MHz, there are means for reducing the uncertainty range to some hundred kHz. Despite this, for a minimum symbol frequency of 1 MHz, and thus a lock-in range of approximately 1 kHz, some hundred frequency trials have to be performed, each trial having to be performed for a few thousands of symbols. As a result, the locking times may reach one second.